|
Lora
|
CMSIS Cortex-M0 Device Peripheral Access Layer Header File. This file contains all the peripheral register's definitions, bits definitions and memory mapping for STM32F0xx devices.
More...
Go to the source code of this file.
Classes | |
| struct | ADC_TypeDef |
| Analog to Digital Converter. More... | |
| struct | ADC_Common_TypeDef |
| struct | CAN_TxMailBox_TypeDef |
| Controller Area Network TxMailBox. More... | |
| struct | CAN_FIFOMailBox_TypeDef |
| Controller Area Network FIFOMailBox. More... | |
| struct | CAN_FilterRegister_TypeDef |
| Controller Area Network FilterRegister. More... | |
| struct | CAN_TypeDef |
| Controller Area Network. More... | |
| struct | CEC_TypeDef |
| HDMI-CEC. More... | |
| struct | COMP_TypeDef |
| Comparator. More... | |
| struct | COMP_Common_TypeDef |
| struct | COMP1_2_TypeDef |
| struct | CRC_TypeDef |
| CRC calculation unit. More... | |
| struct | CRS_TypeDef |
| Clock Recovery System. More... | |
| struct | DAC_TypeDef |
| Digital to Analog Converter. More... | |
| struct | DBGMCU_TypeDef |
| Debug MCU. More... | |
| struct | DMA_Channel_TypeDef |
| DMA Controller. More... | |
| struct | DMA_TypeDef |
| struct | EXTI_TypeDef |
| External Interrupt/Event Controller. More... | |
| struct | FLASH_TypeDef |
| FLASH Registers. More... | |
| struct | OB_TypeDef |
| Option Bytes Registers. More... | |
| struct | GPIO_TypeDef |
| General Purpose I/O. More... | |
| struct | SYSCFG_TypeDef |
| SysTem Configuration. More... | |
| struct | I2C_TypeDef |
| Inter-integrated Circuit Interface. More... | |
| struct | IWDG_TypeDef |
| Independent WATCHDOG. More... | |
| struct | PWR_TypeDef |
| Power Control. More... | |
| struct | RCC_TypeDef |
| Reset and Clock Control. More... | |
| struct | RTC_TypeDef |
| Real-Time Clock. More... | |
| struct | SPI_TypeDef |
| Serial Peripheral Interface. More... | |
| struct | TIM_TypeDef |
| TIM. More... | |
| struct | TSC_TypeDef |
| Touch Sensing Controller (TSC) More... | |
| struct | USART_TypeDef |
| Universal Synchronous Asynchronous Receiver Transmitter. More... | |
| struct | USB_TypeDef |
| Universal Serial Bus Full Speed Device. More... | |
| struct | WWDG_TypeDef |
| Window WATCHDOG. More... | |
Enumerations | |
| enum | IRQn_Type { NonMaskableInt_IRQn = -14 , HardFault_IRQn = -13 , SVC_IRQn = -5 , PendSV_IRQn = -2 , SysTick_IRQn = -1 , WWDG_IRQn = 0 , PVD_VDDIO2_IRQn = 1 , RTC_IRQn = 2 , FLASH_IRQn = 3 , RCC_CRS_IRQn = 4 , EXTI0_1_IRQn = 5 , EXTI2_3_IRQn = 6 , EXTI4_15_IRQn = 7 , TSC_IRQn = 8 , DMA1_Channel1_IRQn = 9 , DMA1_Channel2_3_IRQn = 10 , DMA1_Channel4_5_6_7_IRQn = 11 , ADC1_COMP_IRQn = 12 , TIM1_BRK_UP_TRG_COM_IRQn = 13 , TIM1_CC_IRQn = 14 , TIM2_IRQn = 15 , TIM3_IRQn = 16 , TIM6_DAC_IRQn = 17 , TIM7_IRQn = 18 , TIM14_IRQn = 19 , TIM15_IRQn = 20 , TIM16_IRQn = 21 , TIM17_IRQn = 22 , I2C1_IRQn = 23 , I2C2_IRQn = 24 , SPI1_IRQn = 25 , SPI2_IRQn = 26 , USART1_IRQn = 27 , USART2_IRQn = 28 , USART3_4_IRQn = 29 , CEC_CAN_IRQn = 30 , USB_IRQn = 31 } |
| STM32F0xx Interrupt Number Definition, according to the selected device in Library_configuration_section. More... | |
CMSIS Cortex-M0 Device Peripheral Access Layer Header File. This file contains all the peripheral register's definitions, bits definitions and memory mapping for STM32F0xx devices.
This file contains:
This software component is licensed by ST under BSD 3-Clause license, the "License"; You may not use this file except in compliance with the License. You may obtain a copy of the License at: opensource.org/licenses/BSD-3-Clause